I just dug into the Angelia v6.0 code for you, and can find no evidence of any EER support at all. Nowhere in the code is reference made to "EER" or "envelope". There are references to "PWM", but those are all associated with other things, not EER.
Code: Select all
module Angelia(
//clock afc
input _122MHz, //122.88MHz from VCXO
input OSC_10MHZ, //10MHz reference in
output FPGA_PLL, //122.88MHz VCXO contol voltage
//attenuator (DAT-31-SP+)
output ATTN_DATA, //data for input attenuator
output ATTN_DATA_2,
output ATTN_CLK, //clock for input attenuator
output ATTN_CLK_2,
output ATTN_LE, //Latch enable for input attenuator
output ATTN_LE_2,
//rx adc (LTC2208)
input [15:0]INA, //samples from LTC2208
input [15:0]INA_2, //samples from LTC2208 #2
input LTC2208_122MHz, //122.88MHz from LTC2208_122MHz pin
input LTC2208_122MHz_2, //122.88MHz from #2 LTC2208_122MHz pin
input OVERFLOW, //high indicates LTC2208 have overflow
input OVERFLOW_2, //high indicates LTC2208 have overflow
output RAND, //high turns ramdom on
output RAND_2, //high turns ramdom on
output PGA, //high turns LTC2208 internal preamp on
output PGA_2, //high turns LTC2208 internal preamp on
output DITH, //high turns LTC2208 dither on
output DITH_2, //high turns LTC2208 dither on
output SHDN, //x shuts LTC2208 off
output SHDN_2, //x shuts LTC2208 off
//tx adc (AD9744ARU)
output reg DAC_ALC, //sets Tx DAC output level
output reg signed [13:0]DACD, //Tx DAC data bus
//audio codec (TLV320AIC23B)
output CBCLK,
output CLRCIN,
output CLRCOUT,
output CDIN,
output CMCLK, //Master Clock to TLV320
output CMODE, //sets TLV320 mode - I2C or SPI
output nCS, //chip select on TLV320
output MOSI, //SPI data for TLV320
output SSCK, //SPI clock for TLV320
input CDOUT, //Mic data from TLV320
//phy rgmii (KSZ9021RL)
output [3:0]PHY_TX,
output PHY_TX_EN, //PHY Tx enable
output PHY_TX_CLOCK, //PHY Tx data clock
input [3:0]PHY_RX,
input RX_DV, //PHY has data flag
input PHY_RX_CLOCK, //PHY Rx data clock
input PHY_CLK125, //125MHz clock from PHY PLL
input PHY_INT_N, //interrupt (n.c.)
output PHY_RESET_N,
input CLK_25MHZ, //25MHz clock (n.c.)
//phy mdio (KSZ9021RL)
inout PHY_MDIO, //data line to PHY MDIO
output PHY_MDC, //2.5MHz clock to PHY MDIO
//eeprom (25AA02E48T-I/OT)
output SCK, // clock on MAC EEPROM
output SI, // serial in on MAC EEPROM
input SO, // SO on MAC EEPROM
output CS, // CS on MAC EEPROM
//eeprom (M25P16VMW6G)
output NCONFIG, //when high causes FPGA to reload from eeprom EPCS16
//12 bit adc's (ADC78H90CIMT)
output ADCMOSI,
output ADCCLK,
input ADCMISO,
output nADCCS,
//alex/apollo spi
output SPI_SDO, //SPI data to Alex or Apollo
input SPI_SDI, //SPI data from Apollo
output SPI_SCK, //SPI clock to Alex or Apollo
output J15_5, //SPI Rx data load strobe to Alex / Apollo enable
output J15_6, //SPI Tx data load strobe to Alex / Apollo ~reset
//misc. i/o
input PTT, //PTT active low
input KEY_DOT, //dot input from J11
input KEY_DASH, //dash input from J11
output FPGA_PTT, //high turns Q4 on for PTTOUT
input MODE2, //jumper J13 on Angelia, 1 if removed
input ANT_TUNE, //atu
output IO1, //high to mute AF amp
input IO2, //PTT, used by Apollo
//user digital inputs
input IO4,
input IO5,
input IO6,
input IO8,
//user outputs
output USEROUT0,
output USEROUT1,
output USEROUT2,
output USEROUT3,
output USEROUT4,
output USEROUT5,
output USEROUT6,
//debug led's
output Status_LED,
output DEBUG_LED1,
output DEBUG_LED2,
output DEBUG_LED3,
output DEBUG_LED4,
output DEBUG_LED5,
output DEBUG_LED6,
output DEBUG_LED7,
output DEBUG_LED8,
output DEBUG_LED9,
output DEBUG_LED10,
// RAM
output wire RAM_A0,
output wire RAM_A1,
output wire RAM_A2,
output wire RAM_A3,
output wire RAM_A4,
output wire RAM_A5,
output wire RAM_A6,
output wire RAM_A7,
output wire RAM_A8,
output wire RAM_A9,
output wire RAM_A10,
output wire RAM_A11,
output wire RAM_A12,
output wire RAM_A13
);
